VHDL or Verilog For Learning FPGAs? 301
FlyByPC writes "We're in the first stages of designing a course in programmable devices at the university where I work. The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA. I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++. FPGAs, though, are new to me (although they look very interesting.) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely? (...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?) At this point, I've only seen a little of both languages, so I have no real preference. Any input, especially if you're using one or both in the field, would be very helpful. Thanks, and may all of your K-maps be glitch-free."
don't focus on the language (Score:3, Insightful)
First mistake I always find in these courses is to focus on the language, and not on the skills necesary to make full use of them. I would actually focus the course on your existing schematic and know-how, and bring in the languages used later on, preferably both presented alongside such as SystemC. But that know-how will be far more valuable than any single language possibly can be.
Learn Both (Score:3, Insightful)
Learn Both, and add System Verilog to the list. (Score:3, Insightful)
Learn both, but start with Verilog. Many of VHDL's features are a bit academic, but once you know what is relevant from Verilog it makes it easier to find the "usable subset" of VHDL that's actually good for FPGA design.
System Verilog is the new kid on the block - they ironed out some of Verilog's oddities and added in some of VHDL's very useful features.
Altera already offer System Verilog support, Xilinx support is apparently on the way.
Verilog is a lot easier to learn in general, but VHDL has a great feature ("Records") which are akin to "structures" in C that Verilog doesn't offer.
System Verilog does, which is why it's on my list to learn next.
One other poster made a good point - learn logic design first, then make the language describe the logic for you.
If you don't have a clear idea in your mind how to map out a design in gates and flipflops, (block diagram on a whiteboard is always good) then you should not start coding in an HDL..
Both languages can lead you down the path of unsynthesizable nonsense that seems to simulate ok..
View from an undergrad (Score:2, Insightful)
Re:Where are you located? (Score:5, Insightful)
Speaking as someone who just got his first Verilog-based design working on a Nexys2 board, I can confidently say that there are two serious mistakes a n00b can make:
1) Thinking of Verilog (or any HDL) as anything like C. Yes, there are semicolons. Yes, you can write a "for" loop, if you want to synthesize a huge mess. That's about it.
2) Thinking of Verilog as a programming language at all. HDL stands for "Hardware description language," and that's what they are.
Verilog is fun stuff, but it's the hardest thing I've ever taught myself. For those who are trying, I've found the Bhasker books on synthesis to be quite useful, Pong Chu's FPGA Prototyping with Verilog Examples to be reasonably useful, and most of the others to be fairly worthless. Too many books focus on simulation at the expense of synthesis practices, IMO.
Also have just received Richard Haskell's new books [lbebooks.com] on basic and advanced Verilog using the Basys and Nexys2 platforms. They look very good at first glance but I haven't yet had a lot of time to spend with either of them.
Re:Verilog - Hands down (Score:1, Insightful)
My undergraduate also taught us VHDL on Xilinx FPGAs. I haven't written a line of VHDL in 5 years, whereas I've done 4 internships (AMD & ARM) which all required Verilog knowledge and TAed a senior-level FPGA course (in Verilog) for the last 2 years. As far as the majority of industry goes, teaching Verilog will be of more use to your students (in addition to being much less verbose - the scale of their projects likely does not require much of VHDLs additional functionality). Also in the last few years (Verilog-2001), Verilog has addressed many of the shortcomings it had against VHDL. Automatic sensitivity lists, named ports, generate statements, etc.
In TAing this course, I've found Xilinx tends to prefer VHDL (some of their reference documentation and functionality of EDK requires some VHDL knowledge). I believe internally they are a VHDL house. Though this is a mild annoyance (one you many never encounter), I've found students do fine in using their toolchain with verilog.
Verilog - larger market share and dangerous (Score:3, Insightful)
For me Verilog is closer to describing HW and allows an engineer to do what they want. It is like a sports-bike. It will get you there very fast and you can cut a lot of corners. But, watch out or you will be in a ditch pretty quick.
For students, it is most important that they learn HW design before learning Verilog or VHDL. They need to understand the parallel nature of HW, and should be familiar with state machines and Karnaugh map reductions. In general they should not be writing shifters with for loops. Both languages allow you to describe HW that looks OK in simulation and has a whole host of problems after synthesis. I would teach Verilog because the language will not force good design and the students will be forced to learn when their FPGAs have problems. VHDL, on the other hand, will provided training wheels that allows the user to not truly understand what they are doing and still pass the class.
Re:Schmatic layout? (Score:1, Insightful)
Absolutely not. If you want more than just sample logic circuits, schematics are a dead-end.
In my second university year (Electronics Engineering), I chose a semester-long microprocessor design project. They showed us how to make it using schematic, and everybody did it like that. I found it to be a debugging nightmare. Up until one day before the deadline, I couldn't find the bug in the implementation of a particular opcode (It took me about 2 weeks to design & enter the schematic and 4 weeks debugging and fixing things).
That's when I gave up, dumped the whole schematic, started learning Verilog from examples and capturing my design using Verilog instead of schematic. I finished it in more or less 8 hours (and I even slept that night).
As about Verilog vs VHDL, all I can do is send in this link:
http://www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
Either or Neither (Score:2, Insightful)
Thus, an important part of any course on HDL should have a heavy focus on synthesizeable code, with many iterations of seeing not just the "right" way to do things, but why that is the right way and the alternatives wouldn't produce the same (presumably good) hardware as the alternative ways that look or seem similar.
There are many other languages to consider as well that may or may not end up being used widely in industry.. a sampling is...
SystemC
HandelC
BluSpec
Plus, there are many C-to-Verilog, C-to-VHDL or C-to-HW compilers out there that try to jump from sequential code with pragmas etc. to the HW....
In general, I would suggest thinking of this not as a language course, but as a hardware design course where the tools used happen to include a new language (for the students). It would be easy to concentrate on language syntax and end up with students that know syntax, but not how to make good HW descriptions....
Re:Schmatic layout? (Score:3, Insightful)
No one is doing schematic design for FPGAs any more. If you want to teach schematic design, get a schematic capture and layout package and teach PCB design. There are plenty of things to learn at the board-design level, too, and you can teach some of your circuit theory that way if you wish.
learn digital design, then learn syntax (Score:3, Insightful)
The biggest mistake you can make is concentrating on the language and expecting the programming skills will apply to digital design just because the syntax of Verilog looks like the syntax of C (or VHDL looks like Pascal, if you squint a lot). First, learn how to do digital design, then learn how to describe those designs in an HDL. Things might go slightly faster if you are familiar with the syntactic structures (i.e., C coders will feel more comfortable using Verilog), but trying to take the "do-while--if-then-else--for" mentality of a procedural coder and trying to jam it into an FPGA is going to be a painful road to failure.
It's time for a bad analogy! "Hey guys, I have a bunch of novelists whom I want to teach to write medical textbooks. Should I teach them to do it in English, or Spanish?" The answer is "whichever they're more familiar with already... but first teach them medicine."
-=rsw
Re:Something completely different... (Score:1, Insightful)
But 1000 lines of VHDL makes for a really, really tiny design, far smaller than anything implemented in a modern FPGA in a modern product. If you're still using schematic capture, you must still be developing for CPLD-sized devices.
Re:Where are you located? (Score:5, Insightful)
Having now read through the entirety of the comments on this story, the trend I see is that:
A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while
B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and
C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.
Based on that review, I'd say teach your students VHDL. The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.
Verilog 100% No Question (Score:1, Insightful)
Vhdl solves 0 problems with helping a student learn hardware design. From a personal note I don't think anyone should use FPGA's / CPLD's. They don't solve a single problem that can't be done in pure software. Future more what use is it to say make a Train program on a FPGA / CPLD. There is real use for these hardware device.
My prof made it sound like they were the most important devices in the world and I have to disagree with him completely. I would understand 5 - 10 years ago when we simply didn't have the hardware preformance we have now, then a FPGA / CPLD could be useful.
Well VHDL might have a ton of existing libs for it and it might be reconized widely, it's still a horrible and hidious method of hardware design period. We had to do many labs this year using it and really there was no time saved, NONE, and from what we were taught it would make the job easiler!
After spending 4 months with VHDL and then 1 week with Verilog, there's no completion. Verilog is a much much better method of programming FPGA's / CPLD's. Hands down it wins, it's like asking which is better for programming a airport system , Hand Assembling the software using ATT&T syntax in Windows Debug (VHDL) or using C (Verilog). All the labs the entire class did were preformed 1000x faster in Verilog with a much higher level of understanding.
If you have to pick, it's not a question just and answer it's Verilog all the way. VHDL has to retire, it's of no use, it's horrible to work with, it's horrible to use and forget trying to understand it to a decent level. Verilog is very nice to work with and it omits many of the down falls of VHDL.
I would also like to add that doing FPGA / CPLD design is also becoming rather pointless, with the advances in modern computer programming languages and compiler, it's no longer a case of not having a fast software solution. The hardware and the software are no longer seperated by such a huge amount, well there might be a slight and I mean maybe 1 - 5% increase in preformance using a FPGA / CPLD I don't think that becomes enough of a reason for using them anymore. At least not in college and university programs, doing labs where you have to program a game like Tetris or Space Invaders, what does that teach you. What it does is waste hours and hours of dealing with problems and bugs and crappy syntax do get something that doesn't satify any need.
All in all I think the FPGA and the CPLD,except in special cases, have served there purpose and are no longer a good solution to computer and electronic design. Unless someone can make a hardware desciption language that can actually make sense and flow, the FPGA and CPLD's are done.
Thanks
Murdoch
Re:Where are you located? (Score:2, Insightful)
This person has programmed a single board and considers himself knowledgeable?
1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.
2) HDL ARE programming languages. It compiles and then it runs when its placed in its environment just like EVERY program ever written is supposed to do.
Thank you for telling us what your reading to better educate yourself.
@ OP
As someone who has spent A LOT of time using both in university, I would say Verilog is the easiest to learn because its syntax is very closely related to C. VHDL is better if you absolutely must have full control of the resulting performance on the FPGA. Even then its mostly affected by the performance of the compiler.
I prefer Verilog but being able to add VHDL on the resume can't hurt your students. Spend a few weeks on VHDL first then switch to Verilog. Your students will curse you when they find out how much easier Verilog is, but its better the teach the hard way first before the student becomes dependent on the easy way.
Xilinx software (Score:2, Insightful)
Thanks
Visit http://outputlogic.com/ [outputlogic.com] : tools that improve productivity
Re:VHDL == history (Score:5, Insightful)
When I got into verilog, there was no standard method to support Silicon Asic libraries in VHDL, so verilog owned the Asic market.
I've done both, currenly VHDL, but found Verilog easier to use, both for design description and for testbenches. Verilog (or at least Cadence-XL) has always had file read/write access, and a linking setup very reminiscent of the way a C compiler works, that and the fact that it offers an "include" mechanism like C makes it very easy to compile and link in various test "programs" into the whole testbench.
I found it very surprising how difficult this is to do in VHDL actually.
Some designers I know glue TCL scripts in to handle testbench functions instead of doing so natively in VHDL..
Re:Where are you located? (Score:1, Insightful)
BZZZT You agree VHDL is a language. Do you plan on speaking it, or using it to program? It might be a huge mistake to compare it closely with C or C++, but is is absolutely a programming language.
Re:Where are you located? (Score:3, Insightful)
That's the thing. You have an understanding, if not a working knowledge. Logic is probably one of the most important facets of digital circuitry, once you step back from the nitty-gritty.
Re:VHDL == history (Score:5, Insightful)
I've been in the industry as a chip designer since 1995 (board designer for 15 years before that..) I learned Verilog in about 2 days because I knew C thoroughly. My experience applies to someone who is already a designer - which isn't the case here.
I also know that there are some limitations of the original definition of VHDL that make it a pain to use. The strong typing gets in the way of getting the logic described. VHDL natively can't do things like signed arithmetic. That's why you have all those IEEE packages! In other words - the language is extensible - but you pay a price in lack of brevity to describe the hardware you're after.
There are features of 1995 Verilog that also are a curse and a god-send. The assumption that any undefined term is automatically a wire can save you lots of trouble in the creation of the design or bite you in the posterior (where a strongly typed language would save you from yourself.) So Verilog takes on the original K&R attitude of the programmer being smarter than the compiler and knowing what he/she is doing.
No come into the current century and we have System Verilog. System Verilog = Verilog + Vera + the best parts of VHDL (things like generate).
Where VHDL and Verilog were lacking for strong verification methodologies (that in truth were developed years after either language came into being...) System Verilog has been updated to handle this job adequately along with the task of describing the hardware.
The real answer is that you have asked one of those religious war questions - just like VI vs Emacs (Obviously VI is better ;-) Let me give you a URL that you can read about a contest that was held at DAC some years ago - http://www.angelfire.com/in/rajesh52/contest.html [angelfire.com]
I worked for both Yatin and Larry (two of the conspirators in this story) You be the judge of the Verilog/VHDL war.
I also believe there is a very definite geocentric component to these arguments as has been claimed in earlier posts - In the US Verilog is dominant - while in Europe it's VHDL. I can't speak to other continents. ;-)
In my time as a consultant in the field - I've had two projects out of roughly 20 that were VHDL. Now-a-days these tend to be multi-language affairs where we have both VHDL and Verilog mixed together. Modelsim, and the Cadence offerings handle this pretty transparently (can't speak to the Synopsys tools - haven't used them in better than a decade at this point.)
As another data point - the vast majority of reusable IP that I've seen was done in Verilog. (This may be due to the geographic component - mostly US companies.. ARM being the exception - but everything I see from them is primarily in Verilog... ;-)
Okay - that's lots of data as to what you should do - I would think you should concentrate on teaching about the synthesis subset, proper digital design AND how to write verification environments before they ever even WORRY about FPGAs. What I've seen are a lot of non-designers getting into FPGA design - and they are clueless about things like clock domain crossing and testing the design in simulation BEFORE they go to the FPGA. The old 90/10 rule applies equally here. Do the homework on the design FIRST with simulation before you try to debug every little problem when it's been realized in hardware as an FPGA. I would imagine that students who are trying to become designers are going to suffer the same pitfalls if not shown the RIGHT way to do things.
Hope this gives you some data. In the long run - whether you use Verilog, VHDL or better yet - System Verilog doesn't matter so much as teaching the proper design and verification methodologies!
First ever slashdot contribution (Score:2, Insightful)
Re:Advice from a former instructor of VHDL and FPG (Score:3, Insightful)
Strongly disagree here.
You can do about 99% of what most HDL folks do for FPGAs using Verilog and VHDL. Verilog does it in a more familiar syntax. VHDL requires considerably more pomp and fluff to accomplish the same goals.
It's true that VHDL *may* be more appropriate for bigger, careful projects. But students need to learn principles without tools and other things getting in the way.
Teach principles of HDL with the least roadblocks, then allow more in-depth study to accomplish more. The relatively few students that go on to use what they learn in a class in depth will learn as necessary. If you can get through to ALL of the students using simple tools and languages, then you can teach the fundamentals of HDL and that will stick with them for a long time to come.
Re:Where are you located? (Score:3, Insightful)
Re:Verilog is a programming language (Score:3, Insightful)
Why would you say something as silly as that spice netlist format is not a programming language?
Re:Where are you located? (Score:3, Insightful)
Yes and no. The biggest thing people miss most often is that Verilog used in hardware design is really a subset of the language as a whole. The same is true of VHDL. It can be a programming language. It allows you to program procedurally. You can do your loops and conditionals and function calls, etc. There can be dynamic arrays and dynamic types and file IO.
But none of that is synthesizable. If you want to use Verilog to describe hardware, you have to limit yourself to a fairly small subset. That description is very much not a programming language. The synthesis tool looks at the syntax and "guesses" based on familiar constructs what you're trying to describe. A primary example is a synchronous circuit with an asynchronous reset. You would declare a parallel process (always in Verilog) to trigger on an edge of a clock signal and an edge of a reset.
In reality, an asynchronous reset is level-based but there is no way to describe such a thing in Verilog. The synthesis tool has to recognize the "always @(posedge clk, negedge reset)" construct and know "that's really a level-based asynchronous reset".
It's not just a description of boolean logic. In hardware, one has to consider timing.
Re:System Verilog (Score:3, Insightful)
That is a very dangerous idea. "Let them be sloppy and still make their thing work" may work for software -- where you can just release a patch to fix problems that pop up -- but the primary and most important thing about ASIC design is you only get one shot at it.
That's the first lesson hardware design courses should be teaching. Not making them feel good about how their non-functioning Verilog "program" actually compiles. By the time they actually program it into the FPGA, they should've understood fully how it would translate into gates by the synthesis tool and how it would translate into device-specific macros by the place and route tool.
They should've simulated it at all points of translation as well. VHDL forces you to do this to an extent and that's a good thing.