VHDL or Verilog For Learning FPGAs? 301
FlyByPC writes "We're in the first stages of designing a course in programmable devices at the university where I work. The course will most likely be centered around various small projects implemented on an FPGA dev board, using a Xilinx Spartan3-series FPGA. I have a bit of experience working with technologies from 7400-series chips (designing using schematics) to 8-bit microcontrollers to C/C++. FPGAs, though, are new to me (although they look very interesting.) If you were an undergraduate student studying programmable devices (specifically, FPGAs), would you prefer the course be centered on VHDL, Verilog, a little of both, or something else entirely? (...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?) At this point, I've only seen a little of both languages, so I have no real preference. Any input, especially if you're using one or both in the field, would be very helpful. Thanks, and may all of your K-maps be glitch-free."
Where are you located? (Score:5, Interesting)
Personally, I would say that Verilog is more C-like: weakly typed, compact, efficient notation, whereas VHDL is much more Ada-like: strongly typed, often verbose, but can catch errors that the other one can't.
In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.
Personally, I prefer Verilog.
Re:Where are you located? (Score:5, Interesting)
I agree with the above post, though I personally prefer VHDL. That might however have something to do with me having designed ASIC/FPGAs for about 11 years now using VHDL though. :) Both are very powerful languages these days, and I see no problem in teaching a course using both languages, showing how to create the same hardware using different language constructs.
Advice from a former instructor of VHDL and FPGAs (Score:5, Informative)
Beyond HDLs, however, are FPGAs and ASICs (and I've designed using both). Putting the differences between FPGA and ASIC aside, FPGA has some very specific ties to the vendor because of the way the FPGA is architected. Assignment of I/O, synthesis, and most of all timing constraints for guiding the "map place and route" tools for FPGAs are something you won't learn from VHDL alone (e.g. clock domain frequencies, max/min delays, input/output delays, false/multicycle paths, setup and hold times or worst-case timing paths in the design). These are essential to digital design, but not part of the HDL at all (see Synopsys SDC format for more info). In fact, shell scripts, sed/awk, Perl, TCL, Scheme and Python are also essential to know because they glue the various different tools together through scripting, processing of text files, tailing log files, and batching can be critical to being efficient. So is being thorough in understanding log file warnings and errors, timing reports. Electronic Design Automation or EDA tools also have their own idiosyncrasies, and you'll need to develop a stable "reference front-end and back-end design flow" if you haven't already. Do you use an Altera or Xilinx reference board, or an add-on PCI-based FPGA card? And how do you analyze what's coming and going at the interface? All of these questions need to be answered before you really get going on FPGAs. ASICs have an order of magnitude more complications for reasons I won't even discuss, but it just gets harder. So those state machines that you created without K maps will have synthesis pragmas that direct the compiler to create the appropriate state machine (e.g. One-hot for performance, Gray code for lower power, etc.).
Finally, there's the work world. As other posters have mentioned, North America is primarily focused on Verilog while the rest of the world is VHDL. Most synthesizable IP cores for various functions come as Verilog. So, the truth is, you should know both major HDLs, but you would be better off being proficient in Verilog in the real world for the simple reason that it is the present and future (or at least its successors, such as System Verilog, are the future) are for many reasons. Also, in the work world, it's critical to know the major EDA vendor software and to put it on your resume (i.e. Mentor Graphics, Synplicity (for FPGA), Synopsys, in roughly that order, and Cadence and Magma for ASIC) as well as all those scripting and other languages like Perl and TCL that I mentioned. Don't completely ignore VHDL, however.
As an ironic point, there are SystemC compilers for hardware that are becoming more and m
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Strongly disagree here.
You can do about 99% of what most HDL folks do for FPGAs using Verilog and VHDL. Verilog does it in a more familiar syntax. VHDL requires considerably more pomp and fluff to accomplish the same goals.
It's true that VHDL *may* be more appropriate for bigger, careful projects. But students need to learn principles without tools and other things getting in the way.
Teach principles of HDL with the least roadblocks, then allow more in-depth study to accomplish more. The relatively few
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I would also disagree with Jake73's assertion that Verilogs syntax is more familiar. VHDL would be familiar to any who have used Pascal. (And, more to the point, VHDL is obviously a subset of ADA)
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Except that those "tools and stuff that gets in the way" is exactly what they should be learning. Every single VHDL compile error isn't just a "we're being anal" message. It's a disconnect between what the syntax is describing vs the logic that it will translate to. Hardware design is anal; it has to be accurate down to every bit. There is no room for ambiguity and "trusting the compiler".
You can learn more about digital design concepts from VHDL compile errors than a week's worth of trial-and-error debuggi
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Nonsense. Teaching the tool is the job of a vocational program. The theory of HDL will long out-last any particular errors or syntax that come about.
Except in this case the tool is intricately related to the "theory of HDL". This isn't some "sorry, you used \r\n instead of \n" issue. VHDL compile errors are real design issues. Basic issues that every designer needs to understand.
Example:
integer count;
bit [8:0] bus;
always @(posedge clk, negedge reset) begin
if(reset == 0) begin
count = 0;
end else begin
count = count + 1;
end
end
assign bus = count;
This is all
Not in the context of FPGA/HDL synthesis it's not (Score:3, Interesting)
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You can't avoid timing in hardware. It won't work without a clock. Synthesis won't run without specifications on how fast the thing will run.
Re:Where are you located? (Score:5, Insightful)
Speaking as someone who just got his first Verilog-based design working on a Nexys2 board, I can confidently say that there are two serious mistakes a n00b can make:
1) Thinking of Verilog (or any HDL) as anything like C. Yes, there are semicolons. Yes, you can write a "for" loop, if you want to synthesize a huge mess. That's about it.
2) Thinking of Verilog as a programming language at all. HDL stands for "Hardware description language," and that's what they are.
Verilog is fun stuff, but it's the hardest thing I've ever taught myself. For those who are trying, I've found the Bhasker books on synthesis to be quite useful, Pong Chu's FPGA Prototyping with Verilog Examples to be reasonably useful, and most of the others to be fairly worthless. Too many books focus on simulation at the expense of synthesis practices, IMO.
Also have just received Richard Haskell's new books [lbebooks.com] on basic and advanced Verilog using the Basys and Nexys2 platforms. They look very good at first glance but I haven't yet had a lot of time to spend with either of them.
Test Benches (Score:2, Interesting)
I strongly disagree with the idea that these aren't programming languages and that all you need to know about is the synthesizable subset of each language.
I've worked for several years using VHDL for ASIC/FPGA work. Invariably, I spent 2-3 times as long working on the simulation / test-bench as I did on the VHDL that was actually synthesized into the product. There are a lot of very interesting language features that you can exploit to make the testing more flexible and easy. If you trie
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This person has programmed a single board and considers himself knowledgeable?
1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.
2) HDL ARE programming languages. It compiles and then it runs when its placed in its environment just like EVERY program ever written is supposed to do.
Thank you for telling us what your reading to better educate yourself.
@ OP
As someone who has spent A LOT of time using both in university, I
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1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.
The operators are the same as C operators, the comment style is the same and there are semicolons. That is the full extent of the similarity with C. The are no braces (well, there are, but they don't mean what they do in C), macros are different, constants are different, assignment can be different, functions aren't functions, switch statements are case statements, etc, etc... saying that Verilog is "C like" is only going to confuse people who know C. Verilog has more in common with VHDL that with C really
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Verilog is C-like in that it won't lift much of a finger to keep you from shooting yourself in the foot, and it leaves plenty of ammo lying around. With VHDL the language forces you to specify things much more clearly (and verbosely) up-front. If you're going to compare Verilog to C, then you can compare VHDL to Pascal and its ilk. (Or Ada, as someone else said.) Far from a perfect analogy, but also far from incorrect.
I've used both. I first tried learning Verilog by using it for a few months. Then I
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As someone who has spent A LOT of time using both in university, I would say Verilog is the easiest to learn because its syntax is very closely related to C.
Doing FPGA or ASIC designs?
1) The syntax is incredibly similar to C. Which is why it is always described as "C like" to people who have very little experience in HDL.
Syntax doth not a language make.
Consider Xilinx System Generator (Score:2, Interesting)
It has hand-coded VHDL equivalents for each Simulink function. Generate testbenches, hardware in the loop, etc. You can merge it directly with your own code by writing a simple high level wrapper. It interfaces easily with Chipscope as well (generates files to label eac
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Why not think of Verilog as a programming language? It has to be the right one though. For example, compare it to Prolog. When you describe the hardware in VHDL or Verilog you are essentially describing the logical rules embodied in the hardware, rather than the process that the logic actually represents. Prolog is a lot closer to this model than a procedural or OO language like C or C++. The key is to step away from a flow-control process model to a set-based logic model mapping inputs to outputs. That doe
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Yes and no. The biggest thing people miss most often is that Verilog used in hardware design is really a subset of the language as a whole. The same is true of VHDL. It can be a programming language. It allows you to program procedurally. You can do your loops and conditionals and function calls, etc. There can be dynamic arrays and dynamic types and file IO.
But none of that is synthesizable. If you want to use Verilog to describe hardware, you have to limit yourself to a fairly small subset. That descripti
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Snap.
Agreed.
I see a lot of these "Software programmers don't understand this" posts, on newsgroups etc. I found verilog easy to understand, and I was very much a software programmer. Perhaps in days of yore when C programmers had simple single-threaded code it was appropriate, but the application my team is currently working on frequently has 100 threads or so concurrently running. Constructing an 'always@' block around some signal *is* pretty similar to how we multithread programs these days...
Once you've
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That's the thing. You have an understanding, if not a working knowledge. Logic is probably one of the most important facets of digital circuitry, once you step back from the nitty-gritty.
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That's just mixing semantics. The reality is, from a computer architect's world, there is a clear separation between "programs" and "logic". Programs have the features:
1. They are made up of a finite set of instructions.
2. They can be arbitrarily as big depending on available storage.
3. They control functionality.
HDL's don't create this without some help. You can take an HDL description of hardware and emulate it in software, yes. And you'd have a program. But at the end of the day, synthesis turns it into
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Program Language Interface provides a programmer with transferring control from Verilog to a program function written in C language. It is officially deprecated by IEEE Std 1364-2005 in favor of the newer Verilog Procedural Interface, which completely replaces the PLI.
The PLI ena
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Why would you say something as silly as that spice netlist format is not a programming language?
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In industry, as far as I can tell, Verilog seems to be more used in North America and VHDL in Europe, so that might affect what you care about, too.
When I worked at (UK-based processor designers) ARM [arm.com], Verilog was the language of choice. I've been told VHDL is popular in academia, while Verilog is more popular in industry.
That said, the underlying concepts are pretty similar, and those are what you're teaching really, so either choice would be reasonable.
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Verilog is more popular in the ASIC design industry, for certain. But I work at a large test instrument manufacturer whose products are based heavily on FGPA design, and we are exclusively a VHDL shop.
It is my understanding that Verilog is moving towards stricter type definitions, so that it can get some of the benefits that entails. If you, the submitter, are looking to learn/teach a language least likely to change in the near term, go with VHDL.
That said, a good engineer should be able to sit down with
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YMMV of course, but if I never have to use Xilinx again I'll be glad.
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The biggest problem with Xilinx' compilation software at the moment is their timing analysis. The industry is moving towards system models for timing analysis, based around Synopsys Design Constraints. Their use in ASICs is already pretty common, but for FPGA design their use is pretty new.
Altera's TimeQuest analyzer in their Quartus II software is SDC-based, so learning that gets you the latest and greatest in terms of analysis capabilities. Xilinx still uses classical, chip-centric timing analysis soft
Xilinx software (Score:2, Insightful)
Thanks
Visit http://outputlogic.com/ [outputlogic.com] : tools that improve productivity
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I agree about the industry part, although I find it ironic since VHDL arose from DARPA funded work whereas Verilog is a proprietary innovation turned international standard. At school I learned VHDL though. This wasn't a problem when it came time to use Verilog at work.
My advice: cut against trend. If you're a North American school, use VHDL. If you're in Europe, use Verilog. It may be the only chance for your students to taste the other side.
The insanity of VHDL is attaching two things that you know a
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The insanity of VHDL is attaching two things that you know are 'just wires'. In my experience you spend quite a lot of time writing type-conversion adapters.
OMFG, this annoys the hell out of me. VHDL makes it far too hard to treat numbers as bit-vectors and visa-versa. That and the two incompatible ways of doing maths make Verilog the better choice unless you're forced to use VHDL, IMHO.
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A lot of people compare Verilog to C, and VHDL to Pascal (ADA lite?). Either way I find that a) you will need to know both, if you are going to be in this business, b) Companies that enforce A language, in the US, enforce Verilog, companies that leave it to teams, use either VHDL or Verilog. So if you had to choose just one, and you live in the US, I say choose Verilog ;) That said, the first ASIC I did was in VHDL (which I learned in school). I continued that in single-person FPGAs which I wrote, without o
Re:Where are you located? (Score:5, Insightful)
Having now read through the entirety of the comments on this story, the trend I see is that:
A) students who learned with VHDL then went on to a career with Verilog think the transition was easy and either language is fine, while
B) students who learned with Verilog then went on to a career with VHDL, while rarer, think VHDL is a harder language, and
C) students who were forced to take VHDL when it wasn't in their career plan hated it, because it was so different than a programming language.
Based on that review, I'd say teach your students VHDL. The students that learn it and do well in your course will have the easiest time in the industry, and those that hate it probably won't become good HDL designers regardless.
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I'd agree with the assessment that if this is for students, then always teach the more rigorous language first. This goes for programming languages too. If you teach what is popular today, you end up with graduates who have difficulty adapting in the future. VHDL is the more rigorous and formal language,
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Yep, this is the right attitude. Use the language that has the type checking and strict structure, and then when the shackles come off people have already formed good habits.
I've done about 8 years of VHDL and so prefer it to Verilog, mainly because I'm more familiar with it, but I've had lots of conversations with Verilog engineers over the years saying "You can't do X with VHDL because it's too strict" and it's never true. Learning VHDL was tough, but doing it (and I've got a similar tale with Haskell for
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Also you must learn your synthesis tool. While i'm sure there are cases where code synthisises without any hint as to things being done wrong there are also many cases were it is user error. You really do need to learn how to use timing constraints and the timing analyser that comes with your tool and which warnings are important.
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It's not only where you are, but what part of the industry. From my experience most of the industry (Intel, AMD/ATI, Nvidia, etc) are all Verilog houses. On the other hand anything that interacts with the government (research labs, IBM, defense contractors) are VHDL houses.
But really, it doesn't matter in the long run since there are no fundamental differences between the two. The syntax will take you a month or so to get used to, but the hardware you're designing will be the same. The hard part of hard
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"VHDL was created by hardware engineers who know nothing about programming languages. Verilog was created by computer scientists who know nothing about hardware."
Ummm, no.
Oops, I got the quote backwards (duh), you're right (obviously).
You forgot (Score:2, Funny)
You forgot a few:
Linux vs. *BSD
VI vs. EMACS
Gnome vs KDE
etc.
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You forgot a few:
Linux vs. *BSD
VI vs. EMACS
Gnome vs KDE
etc.
It's emacs vs vi, you insensitive clod!
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You forgot a few:
[--]VI vs. EMACS [--]
etc.
No, he didn't forget that. You see, he wrote:
(...Or is this an eternal, undecidable holy-war question along the lines of ATI/nVidia, AMD/Intel, Coke/Pepsi, etc...?)
... and it's quite clear that VI is the winner.
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and it's quite clear that VI is the winner.
GNU Emacs can simulate vi (Viper-mode). Can Vim simulate Emacs?
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GNU Emacs can simulate vi (Viper-mode). Can Vim simulate Emacs?
sure. :!emacs
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I write my VHDL in Emacs running in a Gnome terminal on BSD, and that's how God intended it!
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Ford vs. GM eh?
No competition here, they'll both be going into bankruptcy soon.
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Ford is in pretty good shape, not because of their truck divisions but because they didn't abandon cars entirely and join their competition in a round of "Americans! Ugrg Ugrg big trucks low mileage screw quality!". While I have only briefly driven them, I understand that the Ford Focus is a rather popular, higher-quality vehicle for its price range. Cars like that saved them more than anything else.
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?? What you state makes no sense. I use VI as my text editor and EMACS as my operating system.
Schmatic layout? (Score:3, Interesting)
I felt like Xilinx Schematic layout was a great first step, because it introduced the circuit theory in a visual way.
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No one is doing schematic design for FPGAs any more. If you want to teach schematic design, get a schematic capture and layout package and teach PCB design. There are plenty of things to learn at the board-design level, too, and you can teach some of your circuit theory that way if you wish.
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The one exception being in the final high-speed I/O stages: serializers, clock generators etc. are better done at the gate level because HDLs still don't give you enough control over time constraints.
don't focus on the language (Score:3, Insightful)
First mistake I always find in these courses is to focus on the language, and not on the skills necesary to make full use of them. I would actually focus the course on your existing schematic and know-how, and bring in the languages used later on, preferably both presented alongside such as SystemC. But that know-how will be far more valuable than any single language possibly can be.
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Absolutely seconded. If you understand:
Interfacing hardware (so the labs can control real world stuff, even if only a LED),
Logic including all kinds of flipflops,
race conditions (folks whom started programing on CPUs always have trouble adjusting to this),
fork/join (and whatever the VHDL equivalent is),
initial vs always (initial as a type of always that only runs once or whatever),
parallel "programming" in general,
computer or other system interfacing,
then, and only then, you're all set to do both Verilog o
VHDL of course (Score:5, Interesting)
Let's put it this way. I once implemented a subset of TCL in pure VHDL to implement feature rich scripting for simulation data. That can't be done in Verilog without dropping out to C.
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Sounds like an argument against VHDL to me... Verilog PLI (programming language interface) was for years one of the things that made verilog better than VHDL. (And it's not just C, there are PLI bindings for scripting languages, too). Not to mention using a simulator like ModelSim you can write Tcl code to interact with the simulation without resorting to tricks like this.
Learn Both (Score:3, Insightful)
Verilog, at least where I work (Score:3, Informative)
I work at a chip company doing ASIC and custom SOC microprocessor stuff. We mostly use verilog here for our stuff. Most of the VHDL I see comes from customers, which often gets blended into our verilog platforms. All our RTL IP cores are verilog that I know of, at least that I've used/seen, and our integration work to make platforms out of all the IP pieces is verilog. What we synthesize to gates is also a verilog gates netlist result that goes to place/route into silicon.
In college the class I took that involved this sort of thing was in VHDL, and I hated that. had me really nto wanting to do this kind of work, I was really happy when I was exposed to verilog and I didn't hate it, and I've been a chip guy for over 10 years now.
But as I understand, VHDL is far more popular in some locations, and verilog in others, so jobs in other locales may be completely opposite to my work environment. It would probably be nice to show some of each to be a little familiar with both such as comparing/contrasting = to = and == to ===, but focus on one or the other for people to really get experience fitting pieces together and learning the general stuff about RTL design, etc. that are not as dependent on what language you use.
Verilog in Silicon Valley (Score:2, Informative)
Learn Both, and add System Verilog to the list. (Score:3, Insightful)
Learn both, but start with Verilog. Many of VHDL's features are a bit academic, but once you know what is relevant from Verilog it makes it easier to find the "usable subset" of VHDL that's actually good for FPGA design.
System Verilog is the new kid on the block - they ironed out some of Verilog's oddities and added in some of VHDL's very useful features.
Altera already offer System Verilog support, Xilinx support is apparently on the way.
Verilog is a lot easier to learn in general, but VHDL has a great feature ("Records") which are akin to "structures" in C that Verilog doesn't offer.
System Verilog does, which is why it's on my list to learn next.
One other poster made a good point - learn logic design first, then make the language describe the logic for you.
If you don't have a clear idea in your mind how to map out a design in gates and flipflops, (block diagram on a whiteboard is always good) then you should not start coding in an HDL..
Both languages can lead you down the path of unsynthesizable nonsense that seems to simulate ok..
VHDL (Score:2, Informative)
View from an undergrad (Score:2, Insightful)
verilog is less of an obstacle (Score:2)
I assume the intent is to teach about how to get your logic into an FPGA, what the internal structures look like, how synthesis maps from language into implementation, etc.
Any good designer has a mental model of what logic is going to get synthesized by a particular snippet of code, I find verilog gets in the way of expressing that model a lot less than VHDL, so I would say verilog is a better choice, in that you can get to the subject you want to teach much faster. Way less time explaining all the VHDL ve
Schematic Capture or Icarus Verilog (Score:3, Informative)
In many ways schematic capture is an easier first step. You can hold off on Verilog or VHDL until you have made every flavor of flip-flop yourself. If you can get logic that has a few to several dozen gates to work first, then you can consider an HDL. And it doesn't really matter too much. There are pros and cons to each, and different industries prefer different languages. Actually different regions of the world prefer different languages too. Verilog is extremely popular in Silicon Valley, but on the East Coast you will find a lot more people using VHDL.
Many who prefer one over another do so because of features for doing verification. Until you know what verification is all about you probably won't be able to make an informed decision.
This fact makes it easy for most people: Icarus Verilog [icarus.com] is open source, free and multi-platform. And useful for doing verification work, and also is capable of generating netlists to use with your favorite Xilinx or Altera parts. I'm not saying it's amazing or anything, but it does have some advantages for a hobbyist doing small projects.
Neither (Score:2)
No really. There are tools for us old timers that let you design at the gate level, and then will create the code for you.
Verilog - larger market share and dangerous (Score:3, Insightful)
For me Verilog is closer to describing HW and allows an engineer to do what they want. It is like a sports-bike. It will get you there very fast and you can cut a lot of corners. But, watch out or you will be in a ditch pretty quick.
For students, it is most important that they learn HW design before learning Verilog or VHDL. They need to understand the parallel nature of HW, and should be familiar with state machines and Karnaugh map reductions. In general they should not be writing shifters with for loops. Both languages allow you to describe HW that looks OK in simulation and has a whole host of problems after synthesis. I would teach Verilog because the language will not force good design and the students will be forced to learn when their FPGAs have problems. VHDL, on the other hand, will provided training wheels that allows the user to not truly understand what they are doing and still pass the class.
VHDL == history (Score:5, Informative)
There were very good reasons why people used VHDL in the past. Because VHDL was an open language before Verilog, the cost of VHDL tools was historically lower than Verilog tools. Since this cost was much more important to FPGA designers, VHDL tended to dominate the FPGA market.
On ASIC side, the first mainstream commercial synthesis tool was Synopsys and Synopsys chose to support Verilog before supporting VHDL. Amongst all the other NRE costs in designing an ASIC, the added cost of using Verilog tools (instead of VHDL) was not really significant. Also, tools to support large designs advanced initially as Verilog tools.
Fast forward few years and Verilog is now open, the cost differential has now disappeared. However, VHDL had a lot of features related to design validation that were not in Verilog. In VHDL you can read and write files. Such things as configurations are supported, etc.. This type of capability makes it easier to write a testbench in VHDL, while on the Verilog side, additional tools and languages are commonly used.
Fast forwards a few more years to today and now we have System Verilog. This gives Verilog the capabilities that it lacked in comparison to VHDL and probably more. The price of VHDL tools is the same as Verilog tools.
Summary: it's clear that the future does not belong to VHDL. It looks like System Verilog is the future, although there are other contenders. So, if the choice is between VHDL and Verilog -- pick Verilog.
Re:VHDL == history (Score:5, Insightful)
When I got into verilog, there was no standard method to support Silicon Asic libraries in VHDL, so verilog owned the Asic market.
I've done both, currenly VHDL, but found Verilog easier to use, both for design description and for testbenches. Verilog (or at least Cadence-XL) has always had file read/write access, and a linking setup very reminiscent of the way a C compiler works, that and the fact that it offers an "include" mechanism like C makes it very easy to compile and link in various test "programs" into the whole testbench.
I found it very surprising how difficult this is to do in VHDL actually.
Some designers I know glue TCL scripts in to handle testbench functions instead of doing so natively in VHDL..
Re:VHDL == history (Score:5, Insightful)
I've been in the industry as a chip designer since 1995 (board designer for 15 years before that..) I learned Verilog in about 2 days because I knew C thoroughly. My experience applies to someone who is already a designer - which isn't the case here.
I also know that there are some limitations of the original definition of VHDL that make it a pain to use. The strong typing gets in the way of getting the logic described. VHDL natively can't do things like signed arithmetic. That's why you have all those IEEE packages! In other words - the language is extensible - but you pay a price in lack of brevity to describe the hardware you're after.
There are features of 1995 Verilog that also are a curse and a god-send. The assumption that any undefined term is automatically a wire can save you lots of trouble in the creation of the design or bite you in the posterior (where a strongly typed language would save you from yourself.) So Verilog takes on the original K&R attitude of the programmer being smarter than the compiler and knowing what he/she is doing.
No come into the current century and we have System Verilog. System Verilog = Verilog + Vera + the best parts of VHDL (things like generate).
Where VHDL and Verilog were lacking for strong verification methodologies (that in truth were developed years after either language came into being...) System Verilog has been updated to handle this job adequately along with the task of describing the hardware.
The real answer is that you have asked one of those religious war questions - just like VI vs Emacs (Obviously VI is better ;-) Let me give you a URL that you can read about a contest that was held at DAC some years ago - http://www.angelfire.com/in/rajesh52/contest.html [angelfire.com]
I worked for both Yatin and Larry (two of the conspirators in this story) You be the judge of the Verilog/VHDL war.
I also believe there is a very definite geocentric component to these arguments as has been claimed in earlier posts - In the US Verilog is dominant - while in Europe it's VHDL. I can't speak to other continents. ;-)
In my time as a consultant in the field - I've had two projects out of roughly 20 that were VHDL. Now-a-days these tend to be multi-language affairs where we have both VHDL and Verilog mixed together. Modelsim, and the Cadence offerings handle this pretty transparently (can't speak to the Synopsys tools - haven't used them in better than a decade at this point.)
As another data point - the vast majority of reusable IP that I've seen was done in Verilog. (This may be due to the geographic component - mostly US companies.. ARM being the exception - but everything I see from them is primarily in Verilog... ;-)
Okay - that's lots of data as to what you should do - I would think you should concentrate on teaching about the synthesis subset, proper digital design AND how to write verification environments before they ever even WORRY about FPGAs. What I've seen are a lot of non-designers getting into FPGA design - and they are clueless about things like clock domain crossing and testing the design in simulation BEFORE they go to the FPGA. The old 90/10 rule applies equally here. Do the homework on the design FIRST with simulation before you try to debug every little problem when it's been realized in hardware as an FPGA. I would imagine that students who are trying to become designers are going to suffer the same pitfalls if not shown the RIGHT way to do things.
Hope this gives you some data. In the long run - whether you use Verilog, VHDL or better yet - System Verilog doesn't matter so much as teaching the proper design and verification methodologies!
how about this approach (Score:2)
Personally we usually look for VHDL programmers instead of verilog - I would recommend focusing primarily on VHDL, touch on Verilog AND maybe expose the students to LabVIEW for FPGA's, or possibly Annapolis Micro's Corefire software just to show them that there are other approaches besides VHDL and Verilog
Either or Neither (Score:2, Insightful)
Thus, an important part of any course on HDL sh
learn digital design, then learn syntax (Score:3, Insightful)
The biggest mistake you can make is concentrating on the language and expecting the programming skills will apply to digital design just because the syntax of Verilog looks like the syntax of C (or VHDL looks like Pascal, if you squint a lot). First, learn how to do digital design, then learn how to describe those designs in an HDL. Things might go slightly faster if you are familiar with the syntactic structures (i.e., C coders will feel more comfortable using Verilog), but trying to take the "do-while--if-then-else--for" mentality of a procedural coder and trying to jam it into an FPGA is going to be a painful road to failure.
It's time for a bad analogy! "Hey guys, I have a bunch of novelists whom I want to teach to write medical textbooks. Should I teach them to do it in English, or Spanish?" The answer is "whichever they're more familiar with already... but first teach them medicine."
-=rsw
System Verilog (Score:2, Interesting)
If your goal is to prevent the students from ever completing their project and running on real hardware, then pick VHDL. Its ADA-like compiler will reject every possible attempt at coding until you master the language.
At least with Verilog you'll compile some gates, which may or may not work functionally, but at least you'll have fun discovering what your code does in hardware.
I was part of the IEEE committee which standardized the VHDL subset for synthesis (a fiasco, but that's another story).
10 years ago,
Re:System Verilog (Score:5, Interesting)
I disagree with the statement that everybody has switched to System Verilog. I've worked with a few companies introducing it, and System Verilog is exactly the reason I want to go back to working with VHDL. It's horrible.
My take on it it is that a load of C++ engineers looked at Verilog and thought "What this needs is object orientation!" completely ignoring the fact that hardware description languages are OO by nature. After all, what is a module if not a method of encapsulating design leaving just a public interface.
The result is a horrible mess of a bi-polar language that can't decide if it's a software language or a hardware one, and the two sides don't really want to talk to each other. Add to that the fact that all of the design patterns that are being used with it are software patterns that don't map well to hardware, that most hardware engineers don't know, and you just get a big steaming pile when you try to introduce it to a company.
The EDA vendors love it because it's giving them a new set of tick boxes they can sell their wares on, but I've yet to see it do anything that I couldn't do in straight verilog / VHDL + a little PLI/FLI, and I've been working as a system verilog application engineer for one of the EDA companies. ...oh and it's really slow (as in orders of magnitude).
Re: (Score:2)
SystemVerilog was largely added for Verification, not design. There are a few constructs that make designing hardware easier than Verilog (enumerations, interface abstracts) but the primary focus of SV is that it allows powerful testbenches.
Before SV, people tested their chips by programming a model in C/C++ and then using a simulator's programming language interface to tie the C model to a Verilog testbench that instantiated their design.
SV makes this rather clunky method go away by introducing C++ like OO
Re: (Score:3, Insightful)
That is a very dangerous idea. "Let them be sloppy and still make their thing work" may work for software -- where you can just release a patch to fix problems that pop up -- but the primary and most important thing about ASIC design is you only get one shot at it.
That's the first lesson hardware design courses should be teaching. Not making them feel good about how their non-functioning Verilog "program" actually compiles. By the time they actually program it into the FPGA, they should've understood fully
A University Student's perspective on VHDL... (Score:2, Informative)
We were introduced to VHDL in our University's Digital Circuits course.
Most of the above commenter's have mentioned that Verilog is C like, I personally have never used or programmed in Verilog so I can't comment on that.
I did however like VHDL very much, particularly because it was *different* from C, I'm kinda growing tired of C like languages and VHDL was a breath of fresh air. It made FPGA's and the entire course in general a whole lot of fun.
It's strong typed nature was a bit cumbersome at first especi
Probably Verilog (Score:2, Informative)
VHDL and Verilog each have their strengths, which is why neither has been able to supplant the other. Perhaps in the long run System Verilog will change this (bringing much of the power of VHDL to the Verilog world), but that day hasn't arrived yet.
Verilog code tends to be very concise, with the language making some implicit conversions and assumptions that turn out to be correct most of the time.
VHDL is bigger, bulkier and more rigid. The rigidity can be annoying, but it also is good at c
go verilog (Score:2)
VHDL is powerful but is too general. Basically, you can make the language do whatever you want, (not just limited to gate code, but any sort of modeling or computation, period), but it's a pain in the ass to do it. Pretty much all the operators and symbols (even '1', '0', 'h', etc) need to be defined before you can do anything, making it a feat to actually get work done. Well, there are standard libraries for stuff, but there are issues with multiply defined symbols and stuff in different libraries.
VHDL is
(Structural) Verilog (Score:2)
Personally I'd go for verilog (Score:2)
VHDL has an incrediablly anal-retentive type system and has some silly ideas like the splitting of entities and architectures. It's also old meaning you need a lot of boilerplate to manually import STD_LOGIC stuff (which is what the synthisis tool vendors tell you to use for everything)
Whichever you use be aware that both VHDL and Verilog weredesigned as hardware simulation languages not hardware synthisis languages. This means it is vital to get to know the synthisis tool you will be using. It is vital to
If you know what you are doing ... (Score:2)
Then the language is almost irrelevant. A good developer, software or hardware, can use just about anything thrown at them to accomplish the task, given a reference manual for the language. FPGAs are just another form of programming and should be treated as such. (Or you could say that software is just an extension of hardware and should be treated as such, doesn't really matter which way it goes).
So, to answer your question. At this point in time, for you, which one you use depends more on non-technica
Simulink (Score:2)
The industry seem to be leaning toward higher-level languages like MATLAB/Simulink, which let you generate automatically VHDL code for your FPGAs from an higher level functional schematic diagram. So you might want to include them perhaps towards the second part the course.
Re: (Score:2)
For signal processing work certainly.
Not for general logic, bus interfacing, state machines etc...
Usually you would end up gluing a Matlab generated core into the middle of a Verilog or VHDL framework, so you need to be able to play in that sandbox..
VHDL=ADA, Verilog=C (Score:2)
If you like the ADA programming language (Yuk!), then choose VHDL. If you prefer the C programming language, then choose Verilog.
Preferences (Score:2)
My first preference would be to have the course taught by someone with real experience with the subject. If it's going to be the blind leading the blind, it's better to not have the course at all.
VIM (Score:2)
VIM
First ever slashdot contribution (Score:2, Insightful)
I like VHDL... Here are some cool reasons why. (Score:2, Informative)
Re: (Score:2)
That's a great post. Even if everything you say is wrong or outdated, it's still a great post. By the time I get all the right answers to the points you raised, I'll know a great deal about the subject that distinguishes experts from dilettantes.
This entire thread is better than average, yet I'm nevertheless somewhat stunned at the number of people equating accessible with good, bloated with bad.
A C program filled with assert() statements is more bloated than a C program without them. I guess it's partly
THUD (Score:2)
Time to shamelessly (neither VHDL nor Verilog) plug THUD [gnuvola.org]. If you are a fan of parentheses (there is an "emacs" tag, above, after all), just imagine your LFSR components nicely bolded [gnuvola.org] and stuff [gnu.org]....
Probably Verilog (Score:2)
Much of the industry appears to be shifting towards Verilog but VHDL is still very common and is not going to disappear any time soon. If I had to make that decision I'd most likely choose Verilog because of this but it's not a simple, clear-cut choice.
When I used to teach Verilog to college seniors & grad students I saw the syntax similarity to C as a problem for many students. Every one of them had a strong programming background and were used to the sequential nature of software. When you let them
I vote Verilog (Score:2)
The answer is both (Score:2)
It's like asking "C++ or Java?". It's not important. What is important is to understand the digital design concepts. Once you've gotten that down, the syntax you need to know in order to design synthesizable circuits in either language is actually quite trivial to learn.
I think Verilog is a cleaner language myself. ASIC designers generally use Verilog whereas VHDL seems to be more dominant in Defense and government designs.
Most good design books will provide both VHDL and Verilog examples. I would highly re
Re: (Score:2)
I work for a company that might be the VHDL-user you mention. I think students who learned VHDL produce code closer to production quality sooner, but it's not very different as you state. Verilog students just need more time to get used to the increased structure requirements of VHDL. I don't ask questions that require either during interviews - the underlying logic of system design is far more important.
If Verilog is moving towards stricter types as I've heard it to be, this difference will close up soo
Re: (Score:2)
Agreed, I started in Verilog (7 + years in industry doing asic and fpga design) then had to learn VHDL.
It was a bit of a steep learning curve (even though I had also used many of the pre Verilog/VHDL languages - palasm, abel, etc).
I've worked with a number of people who started off in VHDL, then found verilog easy and a real treat.
The thing with VHDL is it has far more academic baggage that is of little use in the real design world, but it takes a while to work out what the usable subset of VHDL is, also th
Re: (Score:2)
The odd thing is that Digilent is a VHDL shop. The other product examples are almost exclusively VHDL. So my guess is that Xilinx wrote many of the examples for the XUPV2P (Xilinx University Program Virtex 2 Pro) boards. Xilinx is a mixed shop, with different teams apparently using different languages. (I own a XUPV2P board, but in coursework have only worked with the Nexys and Basys boards.)
Re: (Score:2)
I'm pretty sure Xilinx was once a VHDL house, and is now mostly a mixed house, with the major exception of the EDK team. As such some documentation is still skewed towards VHDL, but if you are not using the EDK, it is not that bad. Besides, VHDL is trivial to read and understand even if you are not familiar with it. (Assuming you are at least familiar with Verilog). (Writing it is definitely harder without being familiar with it).
Re: (Score:2)
Re: (Score:2)
IEEE std_logic_arith for VHDL supports signed arithmetic...